IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
These default status settings may be changed as desired.
After POR, a19–a17, the three most significant bits of the address bus, start with their normal
function, allowing the processor to begin fetching instructions from the boot address FFFF0h.
Normal function is also the default setting for dt/r_n, den_n, and srdy after POR.
If the ad15–ad0 bus override is enabled, s6/clksel1_n and uzi_n/clksel2_n automatically return to
normal operation. The ad15–ad0 bus override is enabled if either the bhe_n/aden_n for the
IA186ER or the rfsh2_n/aden_n for the IA188ER is held low during POR.
4.25 Watchdog Timer
The WDT operates in real WDT fashion and may be used to prevent loss of control in the event
that software does not respond in an expected manner. The WDT is active after reset, has a
maximum timeout count, and is programmed for system reset mode. The WDT control register
(WDTCON) may be written to only once after reset. This is accomplished by writing 3333h,
then CCCCh followed by the new configuration data to the WDTCON register. Provided they
do not include access to the WDTCON register, any number of operations may be performed
between these two words, including memory and I/O reads and writes.
Writing AAAAh then 5555h to the WDTCON register resets the current count. This count
cannot be read. Provided they do not include access to the WDTCON register, any number of
operations may be performed between these two words, including memory and I/O reads and
writes. Use of these sequences is intended to prevent executing code from blocking a WDT
event. With the WDT, a maximum 1.34-second timeout period is possible in a 50-MHz system.
The WDT can be programmed to generate either an NMI or a system reset when it times out. If
programmed to generate an NMI, the NMIFLAG (Bit [12]) in the WDTCON register will be set
when it occurs. This flag should be tested by the NMI interrupt service routine (ISR) to establish
whether the WDT or an external source generated the interrupt. If set by writing the 3333h and
CCCCh sequence followed by the configuration data that includes clearing NMIFLAG, the ISR
should clear this flag. If the NMIFLAG is set while a second WDT timeout occurs, a WDT
system reset is generated in place of a second NMI interrupt.
The RSTFLAG (Bit [13]) in the WDTCON register is set if a WDT reset is generated, due to one
WDT occurrence while the WDT is programmed to generate resets, or because a WDT event
occurred with the NMIFLAG set. This permits system initialization code to distinguish between
a WDT reset and hardware reset and take appropriate action. The RSTFLAG is cleared by a read
or write to the WDTCON register. During a WDT reset, the external pins are not re-sampled,
ensuring that clocking, reset configuration register, and any other features that are user
programmable during reset do not change when a WDT system reset occurs. All other activities
are the same as those of a normal system reset.
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