IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
a0 may be used for address selection, but the timing will be delayed by a half clock cycle over
the timing used for the ucs_n and lcs_n.
4.14 Peripheral Chip Selects
There are six peripheral chip selects (pcs6_n, pcs5_n, and pcs3_n–pcs0_n) that may be used
within a user-defined memory or I/O block. The base address of this user-defined memory block
can be located anywhere within the 1-Mbyte memory address space except for the spaces
associated with the ucs_n, lcs_n, and mcs_n chip selects. Or it may be programmed to the
64 Kbyte I/O space. The pcs4_n pin is not available.
Both the Peripheral Chip Select (PACS) register and the MCS and PCS Auxiliary register
(MPCS) registers are used to program the six peripheral chip selects pcs6_n, pcs5_n, and
pcs3_n–pcs0_n. The PACS register sets the base address, the ready condition, and the wait
states for the pcs3_n–pcs0_n outputs.
The MPCS register configures pcs6_n and pcs5_n pins as either chip selects or address pins a1
and a2, respectively. When these pins are chip selects, the MPCS register also configures them
as being active during memory or I/O bus cycles and their ready condition and wait states.
None of the pcs_n pins are active at reset. Both the Peripheral Chip Select (PACS) register and
the MCS and PCS Auxiliary register (MPCS) registers must be read or written to activate the
pcs_n pins as chip selects.
The pcs6_n and pcs5_n may be programmed to have 0 to 3 wait states, whereas pcs3_n–pcs0_n
may be programmed to have these and 5, 7, 9, or 15 wait states.
4.15 Refresh Control
The Refresh Control Unit (RCU) generates refresh bus cycles. The RCU generates a memory
read request after a programmable period of time to the bus interface unit.
The ENA bit in the Enable RCU register (EDRAM) enables refresh cycles, operating off the
processor internal clock. If the processor is in power-save mode, the RCU must be reconfigured
for the new clock rate.
If the hlda pin is asserted when a refresh request is initiated (indicating a bus hold condition), the
processor disables the hlda pin to allow a refresh cycle to be performed. The external circuit bus
master must deassert the hold signal for at least one clock period to permit the execution of the
refresh cycle.
4.16 Interrupt Control
Interrupt requests originate from a variety of internal and external sources that are arranged by
the internal interrupt controller in priority order and presented one by one to the processor.
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