IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
defined by the control registers. Like the other five registers, these may be changed at any time
(including during a DMA transfer) and are implemented immediately.
4.20 DMA Channel Control Registers
See Section 5.1.9, D1CON (0dah) and D0CON (0cah). The DMA channel control registers
specify the following:
Whether the data destination is in memory or I/O space (Bit [15])
Whether the destination address is incremented, decremented, or unchanged after each
transfer (Bits [14–13])
Whether the data source is in memory or I/O space (Bit [12])
Whether the source address is incremented, decremented, or unchanged after each
transfer (Bits [11–10])
Whether DMA transfers cease upon reaching a designated count (Bit [9])
Whether the last transfer generates an interrupt (Bit [8])
Synchronization mode (Bits [7–6])
The relative priority of one DMA channel with respect to the other (Bit [5])
Acceptance of DMA requests from Timer 2 (Bit [4])
Byte or Word transfers (Bit [0])
4.21 DMA Priority
With the exception of word accesses to odd memory locations or between locked memory
addresses, DMA transfers have a higher priority than CPU transfers. Because the CPU cannot
access memory during a DMA transfer and a DMA transfer cannot be suspended by an interrupt
request, continuous DMA activity will increase interrupt delay. An NMI request halts any DMA
activity, however, enabling the CPU to respond promptly to the request.
4.22 Asynchronous Serial Port
The asynchronous serial port employs standard industry communication protocols in its
implementation of full duplex, bi-directional data transfers. The port can be either the source or
destination of DMA transfers.
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