IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
even if these pins are configured as PIO and enabled (by writing to the MMCS and MPCS
registers for the mcs_n chip selects and to the PACS and MPCS registers for the pcs_n chip
selects), the ready- and wait-state settings for them must agree with those for any overlapping
chip selects as though they were configured as chip selects.
Although pcs4_n is not available as an external pin, it has ready- and wait-state logic and must
follow the rules for overlapping chip-selects. Conversely, pins pcs6_n and pcs5_n have ready-
and wait-state logic that is disabled when configured as address bits a2 and a1, respectively.
Note: If chip-select configuration rules are not followed, the processor may
hang with the appearance of waiting for a ready signal even in a system
where ready (ardy or srdy) is always set to 1.
4.11 Upper Memory Chip Select
The ucs_n chip select is for the top of memory. On reset, the microcontroller begins fetching
and executing instructions at memory location FFFF0h. As a result, upper memory is usually
used for instruction memory. To this end, ucs_n is active on reset and has a memory range of
64 Kbytes (F0000h to FFFFFh) by default, along with external ready required and 3 wait states
automatically inserted. The lower boundary of ucs_n is programmable to provide ranges of 64 to
512 Kbytes.
4.12 Low Memory Chip Select
The lcs_n chip-select is for lower memory. As the interrupt vector table is at the bottom of
memory beginning at 00000h, this pin us usually used for control data memory. Unlike ucs_n,
this pin is inactive on reset, but can be activated by any read or write to the LMCS register.
4.13 Midrange Memory Chip Selects
There are four midrange chip selects, mcs3_n–mcs0_n, which may be used in a user-located
memory block. With some exceptions, the base address of the memory block may be located
anywhere in the 1-Mbyte memory address space (those used by the ucs_n and lcs_n chip selects,
as well as the pcs6_n, pcs5_n, and pcs3_n–pcs0_n, are excluded). If the pcs_n chip selects are
mapped to I/O space, then the MCS address range can overlap the PCS address range.
Both the Midrange Memory Chip Select (MMCS) register and the MCS and PCS auxiliary
(MPCS) registers are used to program the four midrange chip selects. The MPCS register is used
to configure the block size, whereas the MMCS register configures the base address, the ready
condition, and the wait states of the memory block accessed by the mcs_n pin. The chip selects
(mcs3_n–mcs0_n) are activated by performing a write operation of the MMCS and MPCS
registers. The assertion of the MCS outputs occurs with the same timing as the multiplexed AD
address bus (ad15–ad0 on the IA186ER or ao15–ao8 and ad7–ad0 on the IA188ER). The a19–
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