IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
4.9
Ready- and Wait-State Programming
Each of the memory or peripheral chip-select lines can require a ready signal that can be the ardy
or srdy signal. The chip-select control registers (UMCS, LMCS, MMCS, PACS, and MPCS)
each have a single bit that selects whether the external ready signal is to be used or not (R2, Bit
[2]). R1 and R0 (Bits [1–0]) in these registers control the number of wait states that are inserted
during each access to a memory or peripheral location (from 0 to 3). The control registers for
pcs3_n–pcs0_n use three bits, R3, R1–R0 (Bits [3], [1–0]) to provide 5, 7, 9, and 15 wait-states
in addition to the original values of 0 to 3 wait states.
In the case where an external ready has been selected as required, internally programmed wait-
states will always be completed before the external ready can finish or extend a bus cycle. As an
example, consider a system in which the number of wait states to be inserted has been set to 3.
The external ready pin is sampled by the processor during the first wait cycle. The access is
completed after 7 cycles (4 cycles plus 3 wait cycles) if the ready is asserted. Alternatively, if
the ready is not asserted during the first wait cycle, the access is prolonged until ready is asserted
and two more wait states are inserted followed by t4.
4.10 Chip Select Overlap
Overlapping chip selects are configurations where more than one chip select is asserted for the
same physical address. For example, if PCS is configured in I/O space with LCS or any other
chip select configured for memory, address 00000h is not overlapping the chip selects.
Note: It is not recommended that multiple chip-select signals be asserted for
the same physical address, although it may be inescapable in certain
systems. If this is the case, then all overlapping chip-selects must have the
same external ready configuration and the same number of wait states to be
inserted into access cycles.
Internal signals are employed to access the peripheral control block (PCB) and these signals
serve as chip selects that are configured with no wait states and no external ready. Therefore, the
PCB can be programmed with addresses that overlap external chip selects only if these chip
selects are configured in the same manner.
Note: Caution is advised in the use of the DA bit in the LMCS or UMCS
registers when overlapping an additional chip select with either the lcs_n or
ucs_n. Setting the DA bit to 1 prevents the address from being driven onto
the AD bus for all accesses for which the respective chip select is active,
including those for which multiple selects are active.
The mcs_n and pcs_n pins are dual-purpose pins, either as chip selects or PIO inputs or outputs.
However, the respective ready- and wait-state configurations for their chip-select function will
be in effect regardless of the function for which these pins are programmed. This requires that
IA211110517-02
UNCONTROLLED WHEN PRINTED OR COPIED
http://www.innovasic.com
Customer Support:
Page 48 of 146
1-888-824-4184
INNOVASIC [ INNOVASIC, INC ]
