fido2100 3-Port Industrial Ethernet DLR Switch with IEEE1588
Data Sheet
April 10, 2013
timestamp is using 32-bit unsigned arithmetic. At 100MHz the counter will reach the
same value from the starting point in about 42 seconds, and so comparisons are not valid
beyond that. When performing reads, FreeTmr_Lo should be read first, which will cause
the higher 16 bits of the internal Free Timer register to be latched. When FreeTmr_Hi is
read later, the latched value will be returned.
9.2.23 Periodic Interval Timer Register
Mnemonic
type offset bits 15
R/W 0x68
14
13
12
0
11
0
10
0
9
0
9
8
7
6
0
6
5
0
5
0
4
0
4
0
3
0
3
0
2
0
2
0
1
0
1
0
0
0
0
0
PITTmo_Lo
PITTimeout[15:0]
Power-up Defaults
0
0
0
0
8
0
7
Mnemonic
type offset bits 15
R/W 0x6A
14
0
13
0
12
0
11
0
10
0
PITTmo_Hi
PITTimeout[31:16]
Power-up Defaults
0
0
0
0
0
The Periodic Interval Timer register consists of two 16-bit registers. It is a 32-bit down
counter that counts at 50MHz. When the PIT timer is enabled through the pite bit in the
Redundancy Control register, the value from this register is loaded into the timer and
countdown begins. When the timer reaches zero the pit bit in the Switch Event register is
set, and the timer is loaded with value from this register again for the next count down.
To prevent spurious interrupts, this register should be changed only when the pite bit is
reset in the Redundancy Control register. The periodic interval timer can be used to
provide an interrupt to generate ring beacons.
9.2.24 Redundancy Control Register
Mnemonic
type offset bits 15
R/W 0x6C
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Rdndnc_Control
raf drm cns pite p2bte p1bte p2br p1br p2tb p2rb p1tb p1rb rspr dlre resv
Power-up Defaults
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
resv
dlre
Reserved, must be reset (0)
Device Level Ring Protocol Enable. When this bit is set, fido2100 will
support DLR protocol redundancy. If it is reset, fido2100 will not support ring
redundancy.
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