IA186XL/IA188XL
16-Bit Microcontrollers
Data Sheet
July 6, 2011
5.
AC Specifications
5.1
Major Cycle Timings – Read Cycle
TA = -40￮C to +85￮C, VCC = 5V + 10%
All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted.
All output test conditions are with CL = 50 pF.
For AC tests, input VIL = 0.45V and VIH = 2.4V except at X1 where VIH = VCC – 0.5V.
Table 13. Major Cycle Timings – Read Cycle
Values
Min
Symbol
Parameter
Unit Test Conditions
Max
TDVCL
TCLDX
TCHSV
TCHSH
TCLAV
TCLAX
TCLDV
TCHDX
TCHLH
TLHLL
TCHLL
TAVLL
Data in Setup (A/D)
Data in Hold (A/D)
Status Active Delay
Status Inactive Delay
Address Valid Delay
Address Hold
8
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
20
20
20
3
3
0
Data Valid Delay
Status Hold Time
ALE Active Delay
ALE Width
3
20
20
20
10
TCLCL - 15
ALE Inactive Delay
Address Valid to ALE Low
TCLCH - 10
TCHCL - 8
ns
ns
Equal Loading
Equal Loading
TLLAX
Address Hold from ALE Inactive
TAVCH
TCLAZ
Address Valid to Clock High
Address Float Delay
0
ns
ns
ns
ns
ns
ns
TCLAX
20
20
TCLCSV
TCXCSX
TCHCSX
TDXDL
Chip-Select Active Delay
3
Chip-Select Hold from Command Inactive
TCLCH - 10
Equal Loading
Equal Loading
Chip-Select Inactive Delay
DEN Inactive to DT/R Low
3
0
17
TCVCTV
TCVDEX
TCHCTV
TCLLV
TAZRL
TCLRL
TRLRH
TCLRH
TRHLH
Control Active Delay 1
DEN Inactive Delay
Control Active Delay 2
LOCK Valid/Invalid Delay
Address Float to RD Active
RD Active Delay
RD Pulse Width
RD Inactive Delay
RD Inactive to ALE High
3
3
3
3
0
3
17
17
20
17
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
2TCLCL - 15
3
TCLCH - 14
Equal Loading
®
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