IA186XL/IA188XL
16-Bit Microcontrollers
Data Sheet
July 6, 2011
A programmable number of wait states (0 - 3) can be used to generate an internal ready for each
chip select range. The IA186XL can be programmed to use or not use the external ready signal
with or without the internal wait states from the internal ready being factored in.
At reset, the Chip-Select/Ready Logic will be configured as follows:
1. All chip-select outputs will be driven HIGH
2. Exiting RESET, the UCS control register (UMCS) is set to FFFBH, providing chip
select to a 1-Kbyte block of memory with 3 wait states in combined with external
ready.
3. All other chip select control registers are undefined after reset. The CPU must
configure these control registers before the corresponding chips selects will become
active.
4.1.6 DMA
The IA186XL includes a DMA controller with two channels. Transfers can occur between any
combination of Memory and I/O space, to either odd or even address. Data size can be either 8
or 16 bits, except on the IA188XL it can only be 8 bits.
There are separate 20-bit source and destination pointers for each channel. These pointers can be
configured to increment, decrement or stay static after each transfer. For word transfers, pointers
are incremented or decrement by two and for byte transfers, by one. One bus cycle is required to
fetch data and one cycle to deposit it.
4.1.7 DRAM Refresh Control Unit
When in Enhanced Mode, the IA186XL supports DRAM refresh cycles. Reads are
automatically generated at a programmable time interval. If enabled, chip selects are active for
these reads.
4.1.8 Power-Save Control
When in Enhanced Mode, the IA186XL supports a power save mode of operation. The internal
clock frequency is divided by a programmable amount. This affects all internal logic including,
timers, the refresh control unit and clkout generation. Timers and the refresh control unit need to
be reprogrammed accordingly when going in and out of power save if you wish to maintain the
same real time references.
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