IA186XL/IA188XL
16-Bit Microcontrollers
Data Sheet
July 6, 2011
5.2
Major Cycle Timings – Write Cycle
TA = -40￮C to +85￮C, VCC = 5V + 10%
All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted.
All output test conditions are with CL = 50 pF.
For AC tests, input VIL = 0.45V and VIH = 2.4V except at X1 where VIH = VCC – 0.5V.
Table 14. Major Cycle Timings – Write Cycle
Values
Min
Test
Conditions
Symbol
Parameter
Unit
Max
20
TCHSV
TCHSH
TCLAV
TCLAX
TCLDV
TCHDX
TCHLH
TLHLL
TCHLL
Status Active Delay
Status Inactive Delay
Address Valid Delay
Address Hold
3
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
3
20
0
Data Valid Delay
Status Hold Time
ALE Active Delay
ALE Width
3
20
20
20
10
TCLCL - 15
ALE Inactive Delay
TAVLL
TLLAX
Address Valid to ALE Low
TCLCH - 10
TCHCL - 10
ns
ns
Equal Loading
Equal Loading
Address Hold from ALE Inactive
TAVCH
Address Valid to Clock High
Data Hold Time
0
ns
ns
ns
ns
ns
ns
ns
TCLDOX
TCVCTV
TCVCTX
TCLCSV
TCXCSX
TCHCSX
3
Control Active Delay 1
3
20
17
20
Control Inactive Delay
3
Chip-Select Active Delay
Chip-Select Hold from Command Inactive
Chip-Select Inactive Delay
3
TCLCH - 10
3
Equal Loading
Equal Loading
17
17
TDXDL
DEN Inactive to DT/R Low
0
ns
TCLLV
LOCK Valid/Invalid Delay
WR Pulse Width
3
ns
ns
TWLWH
2TCLCL - 15
TWHLH
TWHDX
TWHDEX
WR Inactive to ALE High
Data Hold after WR
TCLCH - 14
TCLCL - 10
TCLCH - 10
ns
ns
ns
Equal Loading
Equal Loading
Equal Loading
WR Inactive to DEN Inactive
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