IA186XL/IA188XL
16-Bit Microcontrollers
Data Sheet
July 6, 2011
5.3
Major Cycle Timings – Interrupt Acknowledge Cycle
TA = -40￮C to +85￮C, VCC = 5V + 10%
All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted.
All output test conditions are with CL = 50 pF.
For AC tests, input VIL = 0.45V and VIH = 2.4V except at X1 where VIH = VCC – 0.5V.
Table 15. Major Cycle Timings – Interrupt Acknowledge Cycle
Values
Test
Conditions
Symbol
Parameter
Unit
Min
8
Max
TDVCL
TCLDX
TCHSV
TCHSH
TCLAV
TAVCH
TCLAX
TCLDV
TCHDX
TCHLH
TLHLL
TCHLL
Data in Setup (A/D)
Data in Hold (A/D)
Status Active Delay
Status Inactive Delay
Address Valid Delay
Address Valid to Clock High
Address Hold
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
3
20
20
20
3
3
0
0
Data Valid Delay
Status Hold Time
ALE Active Delay
ALE Width
3
20
20
20
10
TCLCL - 15
ALE Inactive Delay
Equal
Loading
Equal
TAVLL
TLLAX
Address Valid to ALE Low
TCLCH - 10
TCHCL - 10
ns
ns
Address Hold to ALE Inactive
Loading
TCLAZ
Address Float Delay
Control Active Delay 1
Control Inactive Delay
TCLAX
20
17
17
ns
ns
ns
TCVCTV
TCVCTX
3
3
Equal
Loading
TDXDL
DEN Inactive to DT/R Low
0
ns
TCHCTV
TCVDEX
TCLLV
Control Active Delay 2
3
3
3
20
17
17
ns
ns
ns
DEN Inactive Delay (Non-Write Cycles)
LOCK Valid/Invalid Delay
®
IA211080711-09
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