IA186XL/IA188XL
16-Bit Microcontrollers
Data Sheet
July 6, 2011
Figure 11. Clock Circuit Connection Options
4.1.5 Chip-Select/Ready Generation Logic
The IA186XL provides programmable chip-select generation for memories and peripherals. The
chip can be programmed to provide READY or WAIT state generation. It can also provide
latched address bits A1 and A2. Chip select behavior is the same whether the access is generated
by the CPU or the DMA.
A total of 6 chip selects are dedicated for different memory ranges. A single select for upper
memory (ucs_n), with a fixed end address of 0FFFFH, is good for use as system memory since
the reset vector points to FFFF0H. A single select for lower memory (lcs_n), with a fixed start
address of 0H, is good for interrupt vectors which reside beginning at address 00000H. There
are also four selects for anywhere else (exclusive of ucs_n and lcs_n areas) in the 1 Mbyte
memory in the user-locatable memory block. For the middle chip selects, the base address and
block size are programmable, while only the block size for the upper and lower chip selects are
programmable.
Seven additional chip selects can be programmed to access either peripherals or memory in
seven contiguous fixed blocks of 128 bytes each. A single base address is programmable for
these chip selects.
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