IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
Bits [15–3]—Reserved. Write as 0.
Bit [2–0]—L [2–0] Interrupt Type → The priority or the IS (interrupt service) bit to be
reset is encoded in these three bits. Writing to these bits causes the issuance of an EOI
for the interrupt type (see Table 14, Interrupt Types).
5.1.55 INTVEC (020h) Interrupt Vector Register (Slave Mode)
The CPU shifts left 2 bits (i.e., it multiplies by 4) an 8-bit interrupt type, generated by the
interrupt controller, to produce an offset into the interrupt vector table. The INTVEC register is
undefined at reset (see Table 76).
Table 76. Interrupt Vector Register
15 14 13 12 11 10
9
0
8
0
7
6
5
4
3
2
0
1
0
0
0
0
0
0
0
0
0
T4–T0
Bits [15–8]—Reserved. Read as 0.
Bits [7–3]—T [4–0] Interrupt Type → These five bits contain the five most significant
bits of the types used for the internal interrupt. The least significant three bits of the
interrupt type are supplied by the interrupt controller, as set by the priority level of the
interrupt request.
Bits [2–0]—Reserved. Read as 0.
5.2
Reference Documents
Additional information on the operation and programming of the IA186ES/ IA188ES can be
found in the following AMD publications:
Am186 ES and Am188 ES User’s Manual (Publication 21096).
Am186 ES/ESLV and Am188 ES/ESLV Preliminary Data Sheet (Publication 20002).
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