IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
Table 73. Poll Register
15
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
IREQ
Reserved
S4–S0
Bit [15]—IREQ Interrupt Request → This bit is set to 1 when an interrupt is pending and
during this state, the S4–S0 bits contain valid data.
Bits [14–6]—Reserved.
Bit [4–0]—S [4–0] Poll Status → These bits show the interrupt type of the highest
priority pending interrupt.
5.1.53 EOI (022h) End-Of-Interrupt Register (Master Mode)
The In Service flags of the INSERV register are reset when a write is made to the EOI register.
The interrupt service routine (ISR) should write to the EOI to reset the IS bit, in the INSERV
register, for the interrupt before executing an IRET instruction than ends an interrupt service
routine. Because it is the most secure, the specific EOI reset is the preferred method for resetting
the IS bits. The EOI register is write-only (see Table 74).
Table 74. End-Of-Interrupt Register
15
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
NSPEC
Reserved
S4–S0
Bit [15]—NSPEQ Non-Specific EOI → When set to 1, this bit is a non-specific EOI.
When 0, it indicates the specific EOI.
Bits [14–5]—Reserved.
Bit [4–0]—S [4–0] Source Interrupt Type → These bits show the interrupt type of the
highest priority pending interrupt.
5.1.54 EOI (022h) Specific End-Of-Interrupt Register (Slave Mode)
Specific End-Of-Interrupt Register. An In Service flag of a specific priority in the INSERV
register is reset when a write is made to the EOI register. A three-bit, user-supplied priority-level
value points to the in-service bit that is to be reset. Writing this value to this register resets the
specific bit. Because it is the most secure, the specific EOI reset is the preferred method for
resetting the IS bits. The EOI register is write-only and undefined at reset (see Table 75).
Table 75. Specific End-Of-Interrupt Register
15 14 13 12 11 10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
1
0
0
0
0
0
0
0
L2–L0
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