IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
6.
AC Specifications
Table 77 and Table 78 present the alphabetic and numeric keys to waveform parameters,
respectively. Figure 12 presents the read cycle. Figure 13 presents the multiple read cycles.
Table 79 presents the read cycle timing. Figure 14 presents the write cycle. Table 80 presents
the write cycle timing. Figure 15 presents the multiple write cycles.
Figure 16 presents the PSRAM read cycle. Table 81 presents the PSRAM read cycle timing.
Figure 17 presents the PSRAM write cycle. Table 82 presents the PSRAM write cycle timing.
Figure 18 presents the PSRAM refresh cycle. Table 83 presents the PSRAM refresh cycle
timing. Figure 19 presents the interrupt acknowledge cycle. Table 84 presents the interrupt
acknowledge cycle timing. Figure 20 presents the software halt cycle. Table 85 presents the
software halt cycle timing. Figure 21 presents the active mode. Figure 22 presents the power-
save mode. Table 86 presents the clock timing.
Figure 23 presents the srdy—synchronous ready. Figure 24 presents the ardy—asynchronous
ready. Figure 25 presents the peripherals. Table 87 presents the ready and peripheral timing.
Figure 26 and Figure 27 present Reset 1 and Reset 2, respectively. Figure 28 and Figure 29
present the bus hold entering and bus hold leaving, respectively. Table 88 presents the reset and
bus hold timing.
Table 77. Alphabetic Key to Waveform Parameters
a
a
Min
9
6
Max
–
–
No. Name
Description
49 tARYCH ardy Resolution Transition Setup Time
51 tARYCHL ardy Inactive Holding Time
52 tARYLCL ardy Setup Time
9
–
87 tAVBL
14 tAVCH
12 tAVLL
66 tAVRL
65 tAVWL
24 tAZRL
a Address Valid to whb_n/wlb_n Low
ad Address Valid to Clock High
ad Address Valid to ale Low
a Address Valid to rd_n Low
a Address Valid to wr_n Low
ad Address Float to rd_n Active
tCHCL-1.5
tCHCL
0
–
–
–
–
–
tCHCL
tCLCL+tCHCL
tCLCL+tCHCL
0
45 tCH1CH2 clkouta Rise Time
0
3
68 tCHAV
38 tCHCK
44 tCHCL
clkouta High to a Address Valid
x1 High Time
clkouta High Time
0
7.5
tCLCL/2
8
–
–
67 tCHCSV clkouta High to lcs_n/usc_n Valid
18 tCHCSX mcs_n/pcs_n Inactive Delay
22 tCHCTV Control Active Delay 2
0
0
0
0
0
9
12
10
12
12
64 tCHCV
63 tCHCZ
Command Lines Valid Delay (after Float)
Command Lines Float Delay
a
In nanoseconds.
®
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