IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
Table 78. Numeric Key to Waveform Parameters (Continued)
a
a
No.
14 tAVCH ad Address Valid to Clock High
15 tCLAZ ad Address Float Delay
16 tCLCSV mcs_n/pcs_n Inactive Delay
17 tCXCSX mcs_n/pcs_n Hold from Command Inactive
18 tCHCSX mcs_n/pcs_n Inactive Delay
Name
Description
Min
0
0
Max
–
12
12
–
0
tCLCH
0
0
12
–
19 tDXDL
den_n Inactive to dt/r_n Low
20 tCVCTV Control Active Delay 1
21 tCVDEX den_n Inactive Delay
22 tCHCTV Control Active Delay 2
0
0
0
7.5
0
10
9
10
–
–
10
–
10
–
–
23 tLHAV
24 tAZRL
25 tCLRL
ale High to Address Valid
ad Address Float to rd_n Active
rd_n Active Delay
0
26 tRLRH rd_n Pulse Width
27 tCLRH rd_n Inactive Delay
28 tRHLH rd_n Inactive to ale High
29 tRHAV rd_n Inactive to ad Address Active
30 tCLDOX Data Hold Time
tCLCL
0
tCLCH
tCLCL
0
–
31 tCVCTX Control Inactive Delay
32 tWLWH wr_n Pulse Width
33 tWHLH wr_n Inactive to ale High
34 tWHDX Data Hold after wr_n
35 tWHDEX wr_n Inactive to den_n Inactive
0
10
–
–
–
–
2tCLCL
tCLCH
tCLCL
tCLCH
25
36 tCKIN
37 tCLCK
x1 Period
x1 Low Time
66
–
7.5
38 tCHCK x1 High Time
7.5
–
39 tCKHL
40 tCKLH
x1 Fall Time
x1 Rise time
–
5
5
–
–
–
–
3
3
–
–
–
–
–
–
41 tDSHLH ds_n Inactive to ale Inactive
42 tCLCL clkouta Period
tCLCH
25
43 tCLCH clkouta Low Time
tCLCL/2
44 tCHCL clkouta High Time
tCLCL/2
45 tCH1CH2 clkouta Rise Time
–
–
46 tCL2CL1 clkouta Fall Time
47 tSRYCL srdy Transition Setup Time
48 tCLSRY srdy Transition Hold Time
49 tARYCH ardy Resolution Transition Setup Time
50 tCLARX ardy Active Hold Time
51 tARYCHL ardy Inactive Holding Time
10
3
9
4
6
a
In nanoseconds.
®
IA211050902-19
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