TDA5235
Appendix
Register Description
Field
Bits
Type
Description
MIDFA
2
rc
Interrupt Request by "Message ID Found" from Configuration A
(Reset event sets all Bits to 1)
0B
1B
Not detected
Detected
Reset: 1H
FSYNCA
WUA
1
0
rc
rc
Interrupt Request by "Frame Sync" from Configuration A (Reset
event sets all Bits to 1)
0B
1B
Not detected
Detected
Reset: 1H
Interrupt Request by "Wake Up" from Configuration A (Reset event
sets all Bits to 1)
0B
1B
Not detected
Detected
Reset: 1H
RF PLL Actual Channel and Configuration Register
RFPLLACC
Offset
0AAH
Reset Value
00H
RF PLL Actual Channel and Configuration
Register
ꢀ
ꢃ
ꢈ
ꢄ
ꢅ
ꢆ
ꢇ
ꢁ
5063$&)
*
3/'/(1
8186('
8186('
5063$&
8186('
630$&
U
U
U
U
U
U
U
Field
Bits
Type
Description
PLDLEN
7:6
r
Payload Data Length stored at TSI detection of the next message,
PLDLEN(9:0) = RFPLLACC.PLDLEN(MSB) & PLDLEN(LSB).
Cleared with INIT FIFO
Min. 000h = 0 bits received
Max. 3FFh = 1023 bits received
Reset: 0H
UNUSED
5
4
r
r
UNUSED
Reset: 0H
RMSPACFG
RF PLL Run Mode Self Polling Actual Configuration
0B
1B
Configuration A
Configuration B
Reset: 0H
UNUSED
3
r
UNUSED
Reset: 0H
Data Sheet
249
V1.0, 2010-02-19
INFINEON [ Infineon ]
