TDA5235
Appendix
Register Description
Field
Bits
Type
Description
RSSIPPL
7:0
r
RSSI Peak Level during Payload
Tracking starts after FSYNC + PKBITPOS
Set at every EOM
Cleared at the Reset only
Reset: 00H
Payload Data Length Register
PLDLEN
Offset
0ADH
Reset Value
00H
Payload Data Length Register
ꢀ
ꢁ
3/'/(1
U
Field
Bits
Type
Description
PLDLEN
7:0
r
Payload Data Length stored at TSI detection of the next message,
PLDLEN(9:0) = RFPLLACC.PLDLEN(MSB) & PLDLEN(LSB).
Cleared with INIT FIFO
Min. 000h = 0 bits received
Max. 3FFh = 1023 bits received
Reset: 00H
ADC Result High Byte Register
ADCRESH
Offset
0AEH
Reset Value
00H
ADC Result High Byte Register
ꢀ
ꢁ
$'&5(6+
UF
Field
Bits
Type
Description
ADCRESH
7:0
rc
ADC Result Value ADCRES(9:0) = ADCRESH(7:0) & ADCRESL(1:0)
Note: RC for control signal generation only, no clear
Reset: 00H
Data Sheet
251
V1.0, 2010-02-19
INFINEON [ Infineon ]
