TDA5235
Appendix
Register Description
Field
Bits
Type
Description
TOTIM2NCH
4
w
Continue with next Configuration in Self Polling Mode after TOTIM
detected in Run Mode Self Polling.
0B
1B
Continue with Configuration A in Self Polling Mode
Continue with next Configuration in Self Polling Mode
Reset: 0H
INITFIFO
3
w
Initialization of FIFO at Cycle Start
This Initialization of the FIFO can be configured in both Run Mode Slave
and Self Polling Mode. In Run Mode Slave this happens at the beginning.
In Self Polling Mode the initialization is done after Wake up found
(switching from Self Polling Mode to Run Mode Self Polling).
0B
1B
Initialization disabled
Initialization enabled
Reset: 0H
FSINITFIFO
FIFOLK
2
1
w
w
Initialization of FIFO at Frame Start
0B
1B
Initialization disabled
Initialization enabled
Reset: 1H
Lock Data FIFO at EOM
0B
1B
FIFO lock is disabled
FIFO lock is enabled at EOM. This also locks the digital receive
chain at EOM until release from FIFO lock state.
Reset: 0H
XTALHPMS
0
w
XTAL High Precision Mode in Sleep Mode
0B
1B
Disabled
Enabled
Reset: 0H
Chip Mode Control Register 0
CMC0
Offset
0A6H
Reset Value
10H
Chip Mode Control Register 0
ꢀ
ꢃ
ꢈ
+2/'
Z
ꢄ
ꢅ
8186('
Z
ꢆ
0&6
Z
ꢇ
6/5;(1
Z
ꢁ
06(/
Z
6'2+33(
1
,1,73//
+2/'
&/.287(
1
Z
Z
Z
Field
SDOHPPEN
Bits
Type
Description
7
w
SDO High Power Pad Enable
0B
1B
Normal
High Power
Reset: 0H
Data Sheet
246
V1.0, 2010-02-19
INFINEON [ Infineon ]
