TDA5235
Appendix
Register Description
Field
Bits
Type
Description
RSSIPWU
7:0
-
Peak Detector Level at Wakeup
Set at every WU event and also set at the end of every
configuration/channel cycle within a Self Polling period.
Cleared at Reset only.
Reset: 00H
Interrupt Status Register 0
IS0
Offset
0A8H
Reset Value
FFH
Interrupt Status Register 0
ꢀ
(20%
UF
ꢃ
0,')%
UF
ꢈ
ꢄ
:8%
UF
ꢅ
(20$
UF
ꢆ
0,')$
UF
ꢇ
)6<1&$
UF
ꢁ
:8$
UF
)6<1&%
UF
Field
Bits
Type
Description
EOMB
MIDFB
FSYNCB
WUB
7
rc
Interrupt Request by "End of Message" from Configuration B (Reset
event sets all Bits to 1)
0B
1B
Not detected
Detected
Reset: 1H
6
5
4
3
rc
rc
rc
rc
Interrupt Request by "Message ID Found" from Configuration B
(Reset event sets all Bits to 1)
0B
1B
Not detected
Detected
Reset: 1H
Interrupt Request by "Frame Sync" from Configuration B (Reset
event sets all Bits to 1)
0B
1B
Not detected
Detected
Reset: 1H
Interrupt Request by "Wake Up" from Configuration B (Reset event
sets all Bits to 1)
0B
1B
Not detected
Detected
Reset: 1H
EOMA
Interrupt Request by "End of Message" from Configuration A (Reset
event sets all Bits to 1)
0B
1B
Not detected
Detected
Reset: 1H
Data Sheet
248
V1.0, 2010-02-19
INFINEON [ Infineon ]
