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TDA5235 参数 Datasheet PDF下载

TDA5235图片预览
型号: TDA5235
PDF下载: 下载PDF文件 查看货源
内容描述: 增强灵敏度双配置接收器,具有数字基带处理 [Enhanced Sensitivity Double-Configuration Receiver with Digital Baseband Processing]
分类和应用:
文件页数/大小: 259 页 / 6799 K
品牌: INFINEON [ Infineon ]
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TDA5235  
Appendix  
Register Description  
Field  
Bits  
Type  
Description  
ISAT  
1:0  
w
I Value Saturation. The saturation of the I-Loop-Filter accumulator  
will be set according to the  
ISAT value. Remark that the internal phase resolution of the phase  
detector is 1/16 bit.  
00B saturation to 1/16 bit  
01B saturation to 2/16 bit  
10B saturation to 4/16 bit  
11B saturation to 8/16 bit  
Reset: 1H  
Clock and Data Recovery RUNIN Configuration Register  
A_CDRRI  
Offset  
048H  
Reset Value  
01H  
Clock and Data Recovery RUNIN  
Configuration Register  
'5/,0(1  
Z
8186('  
581/(1  
Z
Field  
Bits  
Type  
Description  
UNUSED  
7:3  
-
UNUSED  
Reset: 00H  
DRLIMEN  
2
w
Enable data rate error acceptance limitation.  
The limits are defined in CDRDRTHRP and CDRDRTHRN registers.  
0B  
1B  
Disabled  
Enabled  
Reset: 0H  
RUNLEN  
1:0  
w
RUNIN Length. The RUNIN length is equal to PLL-start-value  
calculation time. This means  
that the shorter RUNIN length decreases the data rate offset calculation  
accuracy and symbol synchronization found signal generation stability.  
Note that the RUNLEN have to be changed together with the TSI  
configuration registers.  
00B 8 chips  
01B 7 chips  
10B 6 chips  
11B 5 chips  
Reset: 1H  
CDR DC Chip Tolerance Register  
Data Sheet  
214  
V1.0, 2010-02-19  
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