TDA5235
Appendix
Register Description
ꢀ
ꢃ
ꢈ
3+'(1ꢁ
Z
ꢄ
3+'(1ꢀ
Z
ꢅ
ꢆ
ꢇ
ꢁ
3'65
39$/
36$7
Z
Z
Z
Field
Bits
Type
Description
PDSR
7:6
w
Peak-Detector slew rate. The slew rate of the Peak-Detector in the
clock-recovery path will be set with
PDSR. Actually, Peak-Detector part of Signal Detector Block
00B up/down = 1/64
01B up = 1/64; down = 1/128
10B up = 1/32; down = 1/128
11B up = 1/32; down = 1/256
Reset: 3H
PHDEN1
PHDEN0
PVAL
5
w
Phase detector error (PDE) outer tolerance range
0B
1B
Disabled: PDEout = PDEin.
Enabled: If PDEin > abs(7/16) bit then PDEout = 0 else PDEout =
PDEin.
Reset: 1H
4
w
w
Phase detector error (PDE) inner tolerance range
0B
1B
Disabled: PDEout = PDEin.
Enabled: If PDEin < abs(1/16) bit then PDEout = 0 else PDEout =
PDEin.
Reset: 0H
3:2
P Value. The PVAL is the P value of the Clock-Recovery PI Loop-
Filter. The Phase-
Detector output error will be multiplied with the set value.
00B 1/1 phase detector error
01B 1/2 phase detector error
10B 1/4 phase detector error
11B 1/8 phase detector error
Reset: 1H
PSAT
1:0
w
P Value Saturation. The saturation of the P-Loop-Filter path will be
set according to the PSAT
value. Remark that the internal phase resolution of the phase detector is
1/16 bit.
00B saturation to 1/16 bit
01B saturation to 2/16 bit
10B saturation to 4/16 bit
11B saturation to 8/16 bit
Reset: 2H
Clock and Data Recovery Configuration Register
Data Sheet
212
V1.0, 2010-02-19
INFINEON [ Infineon ]
