TDA5235
Appendix
Register Description
Timing Violation Window Register
A_TVWIN
Offset
04BH
Reset Value
28H
Timing Violation Window Register
ꢀ
ꢁ
79:,1
Z
Field
Bits
Type
Description
Timing Violation Window Length.
TVWIN
7:0
w
Defines the maximal number of 1/16 data samples without detected edge
which will be tolerated by CDR with no Loss of Symbol Synchronization
28h: 40/16 bit ((8 + 16 *CV + 8)*1.25)
FFh: 255/16 bit
Note: in TSIGAP mode the value must be higher.
Reset: 28H
Slicer Configuration Register
A_SLCCFG
Offset
04CH
Reset Value
90H
Slicer Configuration Register
ꢀ
ꢁ
6/&&)*
Z
Field
Bits
Type
Description
Data Slicer Configuration
SLCCFG
7:0
w
Value 90H : Chip Mode EOM-CV: For patterns with code violations in data
packet and optimized for activated EOM code violation criterion (and
optional EOM data length criterion)
Value 94H : Chip Mode EOM-Datalength: For patterns with code
violations in data packet and optimized for activated EOM data length
criterion only (EOMDATLEN)
Value 95H : Chip Mode Transparent: When Framer is not used, but
CH_DATA / CH_STR are used for data processing
Value 75H : Bit Mode: Only for patterns without Code Violations
Reset: 90H
Data Sheet
216
V1.0, 2010-02-19
INFINEON [ Infineon ]
