TDA5235
Appendix
Register Description
TSI Detection Mode Register
A_TSIMODE
Offset
04DH
Reset Value
80H
TSI Detection Mode Register
ꢀ
ꢃ
ꢅ
ꢆ
&3+5$
Z
ꢇ
ꢁ
76,*56<
1
76,:&$
76,'(702'
Z
Z
Z
Field
Bits
Type
Description
TSIGRSYN
7
w
TSI Gap Resync Mode (only for TSIDETMODE=2H)
0B
Disabled - In this mode the GAPVAL and TSIGAP values are used,
so the overall GAP time can be
defined in T/16 steps.
1B
Enabled - PLL resync after TSI Gap
In this mode the T/2 GAP resolution can be set in the 5 MSB
TSIGAP register bits.
GAPVAL value is not used. Prefered in TSI Gap Mode.
Reset: 1H
TSIWCA
CPHRA
6:3
2
w
w
w
Wild Cards for 4 LSB chips of Correlator A
If all 4 chips are 0, the whole TSI pattern for Correlator A is valid
if a chip is 1, the corresponding chip from the TSI pattern is ignored
Reset: 0H
Code Phase Readjustment in Payload
0B
1B
disabled - code polarity is defined by the TSI pattern
enabled - code phase readjustment in payload
Reset: 0H
TSIDETMOD 1:0
TSI Detection Mode
00B 16 Bit TSI Mode - TSI configuration B AND A valid (sequentially),
B is valid if A_TSILENA=16 (=10H) and the A_TSILENB > 0
01B 8 Bit Parallel TSI Mode - TSI configurations A OR B (parallel)
10B 8 Bit TSI Gap Mode - TSI configurations A AND B with Gap
(sequentially with Gap between TSIA & TSIB)
11B 8 Bit Extended TSI Mode - TSI configurations A OR B (parallel with
matching information), dependent on found TSI A or B, 0 resp. 1 will
be sent as 1st received bit.
Reset: 0H
TSI Length Register A
A_TSILENA
Offset
04EH
Reset Value
00H
TSI Length Register A
Data Sheet
217
V1.0, 2010-02-19
INFINEON [ Infineon ]
