TDA5235
Appendix
Register Description
Signal Detector Configuration Register
A_SIGDETCFG
Offset
043H
Reset Value
00H
Signal Detector Configuration Register
ꢀ
ꢄ
ꢅ
ꢆ
6'/25(
Z
ꢇ
6'&17ꢁ
Z
ꢁ
6'&17ꢀ
Z
8186('
5HV
ꢂ
Field
Bits
Type
Description
UNUSED
7:4
-
UNUSED
Reset: 0H
SDLORE
2
w
Source selection of Signal Power Readout Register
0B
1B
Signal Power for A_SIGDET0/1
Signal for minimal usable FSK deviation, the sigdet low level can
be read out with SPWR register
Reset: 0H
SDCNT1
SDCNT0
1
0
w
w
Signal Detector Threshold Counter for Wakeup
0B
1B
Disabled
1/2 bit
Reset: 0H
Signal Detector Threshold Counter for Run Mode
0B
1B
Disabled
1/2 bit
Reset: 0H
FSK Noise Detector Threshold Register
A_NDTHRES
Offset
044H
Reset Value
00H
FSK Noise Detector Threshold Register
ꢀ
ꢁ
1'7+5(6
Z
Field
Bits
Type
Description
NDTHRES
7:0
w
FSK Noise Detector Threshold
Reset: 00H
Data Sheet
210
V1.0, 2010-02-19
INFINEON [ Infineon ]
