TC1796
Functional Description
OCDS Level 1 Debug Support
The OCDS Level 1 debug support is mainly assigned for real-time software debugging
purposes which have a demand for low-cost standard debugger hardware.
The OCDS Level 1 debug support is based on a JTAG interface which can be used by
the external debug hardware to communicate with the system. The on-chip Cerberus
module controls the interactions between the JTAG interface and the on-chip modules.
The external debug hardware may become master of the internal buses and read or
write the on-chip register/memory resources. The Cerberus also allows to define
breakpoint and trigger conditions as well as to control user program execution (run/stop,
break, single-step).
OCDS Level 2 Debug Support
The OCDS Level 2 debug support allows to implement program tracing capabilities for
enhanced debuggers by extending the OCDS Level 1 debug functionality with an
additional 16-bit wide trace port with trace clock. With the trace extension the following
four trace capabilities are provided (only one of the four trace capabilities can be
selected at a time):
•
•
•
•
Trace capability of the CPU program flow
Trace capability of the PCP2 program flow
Trace capability of the DMA Controller transaction requests
Trace capability of the DMA Controller move engine status information
OCDS Level 3 Debug Support
The OCDS Level 3 debug support is based on a special emulation device, the
TC1796ED, which provides additional features required for high-end emulation
purposes. The TC1796ED is a device which includes the TC1796 product chip and
additional emulation extension hardware in a package with the same footprint as the
TC1796.
Data Sheet
75
V1.0, 2008-04
INFINEON [ Infineon ]
