TC1796
Electrical Parameters
4.3.12.3 Synchronous Serial Channel (SSC) Master Mode Timing
Table 34
SSC Master Mode Timing (Operating Conditions apply), CL = 50 pF
Parameter
Symbol
Values
Typ.
Unit Note /
Test Con
Min.
Max.
dition
SCLK clock period1)2)
MTSR/SLSOx delay from
SCLK rising edge
t50 CC 2 × TSSC
t51 CC 0
–
–
–
8
ns
ns
–
–
3)
MRST setup to SCLK
falling edge
MRST hold from SCLK
falling edge
t52 SR 10
t53 SR 5
–
–
–
–
ns
ns
–
–
1) SCLK signal rise/fall times are the same as the A2 Pads rise/fall times.
2) SCLK signal high and low times can be minimum 1 × TSSC
.
3) TSSCmin = TSYS = 1/fSYS. When fSYS = 75 MHz, t50 = 26,67ns
t50
SCLK1)2)
t51
t51
MTSR1)
t52
t53
Data
MRST1)
valid
t51
SLSOx2)
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
2) The transition at SLSOx is based on the following setup: SSOTC.TRAIL = 0
and the first SCLK high pulse is in the first one of a transmission.
SSC_Tmg_1.vsd
Figure 44
SSC Master Mode Timing
Data Sheet
129
V1.0, 2008-04
INFINEON [ Infineon ]
