TC1796
Electrical Parameters
4.3.12.2 Micro Second Channel (MSC) Interface Timing
Table 33
MSC Interface Timing (Operating Conditions apply), CL = 50 pF
Parameter
Symbol
Values
Typ.
Unit Note /
Test Con
Min.
Max.
dition
FCLP clock period1)2)
SOP/ENx outputs delay
from FCLP rising edge
t40 CC 2 × TMSC
t45 CC -10
–
–
10
ns
ns
–
–
3)
SDI bit time
SDI rise time
SDI fall time
t46 CC 8 × TMSC
t48 SR
–
100
100
ns
ns
ns
–
–
–
t49 SR
1) FCLP signal rise/fall times are the same as the A2 Pads rise/fall times.
2) FCLP signal high and low can be minimum 1 × TMSC
.
3) TMSCmin = TSYS = 1/fSYS. When fSYS = 75 MHz, t40 = 26,67ns
t40
0.9 VDDP
0.1 VDDP
FCLP
t45
t45
SOP
EN
t48
t49
0.9 VDDP
0.1 VDDP
SDI
t46
t46
MSC_Tmg_1.vsd
Figure 43
MSC Interface Timing
Note: The data at SOP should be sampled with the falling edge of FCLP in the target
device.
Data Sheet
128
V1.0, 2008-04
INFINEON [ Infineon ]
