TC1796
Electrical Parameters
Address
Phase(s)
Command
Phase(s)
Burst
Burst
Recovery
Phase(s)
Next Addr.
Phase(s)
Phase(s)
Phase(s)
BFCLKI
1)
BFCLKO
t10
t10
Next
A[23:0]
ADV
Burst Start Address
Addr.
t22
t22
t22
t10
t10
t10
CS[3:0]
CSCOMB
t12
t12
t22
t24
RD
t22
BAA
t24
t23
t23
D[31:0]
(32-Bit)
Data (Addr+0)
Data (Addr+4)
D[15:0]
(16-Bit)
Data (Addr+0)
Data (Addr+2)
t26
t25
WAIT
1)
Output delays are always referenced to BCLKO. The reference clock for input
characteristics depends on bit EBU_BFCON.FDBKEN.
EBU_BFCON.FDBKEN = 0:BFCLKO is the input reference clock.
EBU_BFCON.FDBKEN = 1:BFCLKI is the input reference clock (EBU clock
feedback enabled).
BurstRD_4.vsd
Figure 40
EBU Burst Mode Read Timing
Data Sheet
124
V1.0, 2008-04
INFINEON [ Infineon ]
