TC39x BC/BD-Step
Pin Definition and Functions: LFBGA-516 Package Variant Pin Configuration
Table 2-10 Port 20 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
N24
P20.2
I
S / PU /
VEXT
General-purpose input
This pin is latched at power on reset release to enter test
mode.
TESTMODE
P20.3
Testmode Enable Input
General-purpose input
Mux input channel 5 of TIM module 4
Mux input channel 4 of TIM module 3
Mux input channel 4 of TIM module 2
Receive input
M25
I
SLOW /
PU1 /
VEXT /
ES
GTM_TIM4_IN5_11
GTM_TIM3_IN4_5
GTM_TIM2_IN4_5
ASCLIN3_ARXC
GPT120_T6INA
P20.3
Trigger/gate input of core timer T6
General-purpose output
GTM muxed output
O0
O1
O2
GTM_TOUT61
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI0_SLSO9
QSPI2_SLSO9
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
CAN21_TXD
—
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Master slave select output
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
I
CAN transmit output node 1
Reserved
L22
P20.6
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 6
Mux input channel 6 of TIM module 3
Mux input channel 6 of TIM module 2
CAN receive input node 2
Receive input
GTM_TIM6_IN0_1
GTM_TIM3_IN6_5
GTM_TIM2_IN6_5
CAN12_RXDA
ASCLIN9_ARXE
P20.6
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT62
ASCLIN1_ARTS
QSPI0_SLSO8
QSPI2_SLSO8
—
Ready to send output
Master slave select output
Master slave select output
Reserved
—
Reserved
—
Reserved
Data Sheet
90
V 1.2, 2021-03
OPEN MARKET VERSION
INFINEON [ Infineon ]
