TC39x BC/BD-Step
Pin Definition and Functions: LFBGA-516 Package Variant Pin Configuration
Table 2-9 Port 15 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
B24
P15.10
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM7_IN0_2
GTM_TIM4_IN1_7
GTM_TIM2_IN1_8
QSPI5_MRSTA
P15.10
Mux input channel 0 of TIM module 7
PU1 /
VEXT /
ES6
Mux input channel 1 of TIM module 4
Mux input channel 1 of TIM module 2
Master SPI data input
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT242
—
Reserved
QSPI5_MRST
MSC3_FCLN
—
Slave SPI data output
Shift-clock inverted part of the differential signal
Reserved
—
Reserved
—
Reserved
A24
P15.11
LVDS_TX General-purpose input
/ FAST /
GTM_TIM7_IN1_2
GTM_TIM4_IN2_6
GTM_TIM2_IN2_8
QSPI5_SLSIA
P15.11
Mux input channel 1 of TIM module 7
PU1 /
VEXT /
ES6
Mux input channel 2 of TIM module 4
Mux input channel 2 of TIM module 2
Slave select input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT243
—
Reserved
QSPI5_SLSO2
MSC3_FCLP
—
Master slave select output
Shift-clock direct part of the differential signal
Reserved
—
Reserved
—
Reserved
B23
P15.12
LVDS_TX General-purpose input
/ FAST /
GTM_TIM7_IN2_2
GTM_TIM4_IN3_6
GTM_TIM2_IN3_6
P15.12
Mux input channel 2 of TIM module 7
PU1 /
VEXT /
ES6
Mux input channel 3 of TIM module 4
Mux input channel 3 of TIM module 2
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT244
—
Reserved
QSPI5_SLSO1
MSC3_SON
—
Master slave select output
Data output - inverted part of the differential signal
Reserved
—
Reserved
—
Reserved
Data Sheet
87
V 1.2, 2021-03
OPEN MARKET VERSION
INFINEON [ Infineon ]
