TC39x BC/BD-Step
Pin Definition and Functions: LFBGA-516 Package Variant Pin Configuration
Table 2-9 Port 15 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
A23
P15.13
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM7_IN3_3
GTM_TIM4_IN4_6
GTM_TIM2_IN4_9
P15.13
Mux input channel 3 of TIM module 7
PU1 /
VEXT /
ES6
Mux input channel 4 of TIM module 4
Mux input channel 4 of TIM module 2
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT245
—
Reserved
QSPI5_SLSO0
MSC3_SOP
—
Master slave select output
Data output - direct part of the differential signal
Reserved
—
Reserved
—
Reserved
B22
P15.14
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 7
Mux input channel 5 of TIM module 4
Mux input channel 5 of TIM module 2
Slave SPI data input
General-purpose output
GTM muxed output
GTM_TIM7_IN4_2
GTM_TIM4_IN5_6
GTM_TIM2_IN5_12
QSPI5_MTSRA
P15.14
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT246
—
Reserved
QSPI5_MTSR
MSC3_EN0
—
Master SPI data output
Chip Select
Reserved
—
Reserved
—
Reserved
A22
P15.15
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 7
Mux input channel 6 of TIM module 4
Mux input channel 6 of TIM module 2
Slave SPI clock inputs
General-purpose output
GTM muxed output
GTM_TIM7_IN5_2
GTM_TIM4_IN6_6
GTM_TIM2_IN6_9
QSPI5_SCLKA
P15.15
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT247
—
Reserved
QSPI5_SCLK
MSC3_EN1
—
Master SPI clock output
Chip Select
Reserved
—
Reserved
—
Reserved
Data Sheet
88
V 1.2, 2021-03
OPEN MARKET VERSION
INFINEON [ Infineon ]
