TC39x BC/BD-Step
Electrical SpecificationPower Supply Infrastructure and Supply Start-up
3.13.1.3 External Supply mode (d)
VEXT (externally supplied)
0
1
2
3
4
5
5.5 V
5.0 V
4.5 V
LVD Reset release
HWCFG[1,2] latch
VRST5
Primary cold PORST Reset Threshold
LVD Reset Threshold
VLVDRST5
VDDPPA
0 V
HWCFG[6] latch
VDD (externally supplied)
1.375 V
1.25 V
VRSTC
Primary Reset Threshold
0 V
PORST output deasserted when VDD,
VDDP3 and VEXT voltage above
respective primary reset thresholds
PORST (output driven by PMS)
PORST (input driven by external regulator)
PORST input deasserted by external
regulator when all input voltages have
reached their minimum operational level
VDDP3 (internally generated
by EVR33)
3.63 V
3.30 V
VRST33
Primary Reset Threshold
tEVRstartup
(incl. tSTR)
EVR33 is started with a delay after
VLVDRST5 level is reached at VEXT &
VLVDRSTC level is reached at VDDPD
EVR33_tSTR
0 V
tBP (incl. tEVRstartup)
T1
T0
T3
T2
T4
User Code Execution
fCPU0=100MHz default
on firmware exit
T5
Basic Supply & Clock
Infrastructure
EVR33 Ramp-up Phase
Firmware Execution
Power Ramp-down phase
Startup_Diag_1 v 0.3
Figure 3-5 External Supply mode (d) - VEXT and VDD externally supplied
VEXT = 5 V and VDD supplies are externally supplied. 3.3V is generated internally by the EVR33 regulator.
•
External supplies VEXT and VDD may ramp-up or ramp-down independent of each other with regards to start,
rise and fall time(s). Start-up slew rates for supply rails shall comply to datasheet parameter SR. The slope is
defined as the maximal tangential slope between 0% to 100% voltage level. Actual waveform may not
represent the specification. It is expected that during start-up, VEXT ramps up before VDD rail. If VDD voltage
Data Sheet
458
V 1.2, 2021-03
OPEN MARKET VERSION
INFINEON [ Infineon ]
