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    SAK-TC399XP-256F300S BC 参数 Datasheet PDF下载

    SAK-TC399XP-256F300S BC图片预览
    型号： SAK-TC399XP-256F300S BC
    PDF下载： 下载PDF文件 查看货源
    内容描述： [Infineon releases its second generation AURIX microcontroller in embedded flash 40 nm technology. It comes back with an increase in performance, memory sizes, connectivity and more scalability to address the new automotive trends and challenges. This family has more than 20 products to provide the most scalable portfolio of safety microcontrol­ler. In terms of performance, the highest end product TC39x offers 6 cores running at 300 MHz and up to 6.9 MBytes embedded RAM, and consuming below 2 W. ]
    分类和应用：
    文件页数/大小： 548 页 / 21256 K
    品牌： INFINEON [ Infineon ]
     浏览型号SAK-TC399XP-256F300S BC的Datasheet PDF文件第458页浏览型号SAK-TC399XP-256F300S BC的Datasheet PDF文件第459页浏览型号SAK-TC399XP-256F300S BC的Datasheet PDF文件第460页浏览型号SAK-TC399XP-256F300S BC的Datasheet PDF文件第461页浏览型号SAK-TC399XP-256F300S BC的Datasheet PDF文件第463页浏览型号SAK-TC399XP-256F300S BC的Datasheet PDF文件第464页浏览型号SAK-TC399XP-256F300S BC的Datasheet PDF文件第465页浏览型号SAK-TC399XP-256F300S BC的Datasheet PDF文件第466页  
    TC39x BC/BD-Step  
    Electrical SpecificationReset Timing  
    3.14  
    Reset Timing  
    Table 3-30 Reset  
    Parameter  
    Symbol  
    Values  
    Typ.  
    Unit  
    Note / Test Condition  
    Min.  
    Max.  
    Application Reset Boot Time  
    System Reset Boot Time  
    tB CC  
    -
    -
    400  
    µs  
    operating with max.  
    frequencies, with valid  
    BMI header  
    t
    BS CC  
    -
    -
    -
    1.1  
    3.1  
    ms  
    ms  
    RAM initialization and  
    HSM boot time are not  
    included, with valid BMI  
    header  
    Cold Power on Reset Boot Time tBP CC  
    -
    dVEXT/dT=1V/ms.  
    VEXT>VLVDRST5.  
    Boot time after Cold  
    PORST including EVR  
    ramp-up and Firmware  
    execution time; RAM  
    initialization and HSM  
    boot time are not  
    1)  
    included.  
    -
    -
    -
    1.6  
    ms  
    Firmware execution  
    time after PORST  
    release without EVR  
    ramp-up; RAM  
    initialization and HSM  
    boot time is not  
    included  
    Minimum cold PORST reset  
    hold time in case of power fail  
    event issued by EVR primary  
    monitors  
    t
    EVRPOR CC 10 2)  
    -
    µs  
    PMS Infrastructure, EVRC and tEVRstartup  
    EVR33 overall start-up time till CC  
    cold PORST reset release  
    -
    -
    -
    1
    -
    ms  
    ms  
    dV/dT=1V/ms. EVRC  
    and EVR33 active  
    Minimum PORST active hold  
    time externally after power  
    supplies are stable at operating  
    levels after start-up  
    t
    POA SR  
    1 3)  
    Configurable PORST digital  
    filter delay in addition to analog  
    pad filter delay  
    t
    PORSTDF CC 600  
    -
    1200  
    ns  
    Warm Reset Sequencing Delay tWARMRSTSEQ  
    -
    -
    -
    180  
    -
    µs  
    ns  
    CC  
    HWCFG pins hold time from  
    ESR0 rising edge  
    t
    HDH CC  
    16 / fSPB  
    Data Sheet  
    462  
    V 1.2, 2021-03  
    OPEN MARKET VERSION  

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