TC39x BC/BD-Step
Electrical SpecificationPower Supply Infrastructure and Supply Start-up
3.13.1.4 External Supply mode (h)
VEXT (externally supplied)
0
1
3
4
5
5.5 V
5.0 V
4.5 V
LVD Reset release
HWCFG[1,2] latch
VRST5
Primary cold PORST Reset Threshold
LVD Reset Threshold
VLVDRST5
VDDPPA
0 V
HWCFG[6] latch
VDD (externally supplied)
1.375 V
1.25 V
VRSTC
Primary Reset Threshold
0 V
VDDP3
(externally supplied)
3.63 V
3.30 V
VRST33
Primary Reset Threshold
0 V
PORST output deasserted when VDD,
VDDP3 and VEXT voltage above
respective primary reset thresholds
tPOA time to ensure adequate time between reset releases
PORST (input driven by external regulator)
PORST (output driven by PMS)
tBP
T3
T0
T1
T4
T5
User Code Execution
fCPU0=100MHz default
on firmware exit
Basic Supply & Clock
Infrastructure
Firmware Execution
Power Ramp-down phase
Startup_Diag_3 v 0.4
Figure 3-6 External Supply mode (h) - VEXT, VDDP3 & VDD externally supplied
All supplies, namely VEXT, VDDP3 & VDD are externally supplied.
•
External supplies VEXT, VDDP3 & VDD may ramp-up or ramp-down independent of each other with regards
to start, rise and fall time(s). Start-up slew rates for supply rails shall comply to datasheet parameter SR. The
slope is defined as the maximal tangential slope between 0% to 100% voltage level. Actual waveform may not
represent the specification. It is expected that during start-up, VEXT ramps up before VDDP3 and VDD rails.
If smaller voltage rails are ramped up before VEXT; VDD and VDDP3 supply overshoots during start-up shall
be limited within the operational voltage ranges of the respective rails.
Data Sheet
460
V 1.2, 2021-03
OPEN MARKET VERSION
INFINEON [ Infineon ]
