TC39x BC/BD-Step
Electrical SpecificationPower Supply Infrastructure and Supply Start-up
VEXT = 5 V single supply mode. VDD and VDDP3 are generated internally by the EVRC and EVR33 internal
regulators.
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The rate at which current is drawn from the external regulator (dIEXT /dt) is limited during the basic
infrastructure and EVRx regulator start-up phase (T0 up to T2) to a maximum of 100 mA with 100 us settling
time. Start-up slew rates for supply rails shall comply to datasheet parameter SR. The slope is defined as the
maximal tangential slope between 0% to 100% voltage level. Actual waveform may not represent the
specification.
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Furthermore it is also ensured that the current drawn from the regulator (dIDD/dt) is limited during the Firmware
start-up phase (T3 up to T4) to a maximum of 100 mA with 100 us settling time.
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PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It
is recommended to keep the PORST (input) asserted until the external supply is above the respective primary
reset threshold.
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PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus
propagating the reset to external devices. The PORST (output) is asserted by the µC when atleast one among
the three supply domains (VDD, VDDP3 or VEXT) violate their primary under-voltage reset thresholds.The
PORST (output) is de-asserted by the µC when all supplies are above their primary reset thresholds and the
basic supply and clock infrastructure is available. During reset release at T3, the load jump of upto 150 mA
(dIDD) is expected.
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The power sequence as shown in Figure 3-3 is enumerated below
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T1 up to T2 refers to the period in time when basic supply and clock infrastructure components are
available as the external supply ramps up. The bandgap and internal clock sources are started .The supply
mode is evaluated based on the HWCFG[2:1,4,5,6] and TESTMODE pins. T1 up to T2 refers to the period
in time when basic supply and clock infrastructure components are available as the external supply ramps
up. The bandgap and internal clock sources are started .The supply mode is evaluated based on the
HWCFG[2:1,6] pins. These events are initiated after LVD reset release at T1. LVD reset is released the
both input voltages VEXT and VEVRSB are above VLVDRST5 and VLVDRSTSB levels correspondingly.
Internal pre-regulator VDDPD output voltage is above VLVDRSTC level.
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T2 refers to the point in time where consequently a soft start of EVRC and EVR33 regulators are initiated.
PORST (input) does not have any affect on EVR33 or EVRC output and regulators continue to generate
the respective voltages though PORST is asserted and the device is in reset state. The generated voltage
follows a soft ramp-up over the tSTR (datasheet parameter) time to avoid overshoots.
T3 refers to the point in time when all supplies are above their primary reset thresholds denoted by VRST5,
VRST33 and VRSTC supply voltage levels. EVRC and EVR33 regulators have ramped up.
PORST (output) is de-asserted and HWCFG[3:5] pins are latched on PORST rising edge by SCU.
Firmware execution is initiated. The time between T1 and T3 is documented as tEVRstartup (datasheet
parameter).
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T4 refers to the point in time when Firmware execution is completed and User code execution starts with
CPU0 at a default frequency of 100 MHz. The time between T0 and T4 is documented as tBP (datasheet
parameter).
T5 refers to the point in time during the ramp-down phase when at least one of the externally provided or
generated supplies (VDD, VDDP3 or VEXT) drop below their respective primary under-voltage reset
thresholds.
Data Sheet
455
V 1.2, 2021-03
OPEN MARKET VERSION
INFINEON [ Infineon ]
