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SAK-TC399XP-256F300S BC 参数 Datasheet PDF下载

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型号: SAK-TC399XP-256F300S BC
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内容描述: [Infineon releases its second generation AURIX microcontroller in embedded flash 40 nm technology. It comes back with an increase in performance, memory sizes, connectivity and more scalability to address the new automotive trends and challenges. This family has more than 20 products to provide the most scalable portfolio of safety microcontrol­ler. In terms of performance, the highest end product TC39x offers 6 cores running at 300 MHz and up to 6.9 MBytes embedded RAM, and consuming below 2 W. ]
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文件页数/大小: 548 页 / 21256 K
品牌: INFINEON [ Infineon ]
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TC39x BC/BD-Step  
Electrical SpecificationPower Supply Current  
Table 3-29 Module Core Current Consumption (cont’d)  
Parameter  
Symbol  
Values  
Typ.  
Unit  
Note / Test Condition  
Min.  
Max.  
I
DD core dynamic current load  
IDDSPULJ2  
-
-
310 3)  
mA  
CTRL.DIV = 00; SPU  
@ 300 MHz; FFT  
length 512;  
jump during IDDSPU2 pattern. CC  
DATSRC=EMEM;  
complex windowing  
I
DD core dynamic current added IDDLBIST CC  
by LBIST  
DD core dynamic current added IDDMBIST CC -  
by MBIST  
-
-
-
150 4)  
225  
mA  
mA  
LBIST Configuration A;  
1.2V ≤ VDD  
I
fMBIST = 300MHz;  
tMBIST < 6ms. MTU  
Ganging procedure for  
SRAM test and  
initialization; VDD =  
1.375V.  
1) The current consumption includes basic HSM activity incl. AES module.  
2) The current is estimated as the sum of the SPU base load current at clock activation and average current caused by SPU  
dynamic activity as defined in the conditions. Secondary Voltage Monitor over-voltage threshold shall be set to VDD + 10%  
and under-voltage threshold shall be set to VDD - 9% respectively.  
During the SPU operational phase for IDDSPU1/2 usecase, the externally supplied VDD voltage has to be equal or greater than  
1.225V (VDD nominal - 2%) for static accuracy part and the overall static and dynamic at the VDD supply pin shall be limited to  
(VDD nominal -8%).  
3) The dynamic current load jump during SPU activity as defined by the conditions observed at the VDD pin beyond a settling  
time duration of 20 us.  
4) LBIST is executed either during start-up phase or can be triggered by application software. Secondary voltage monitors are  
inactive during the LBIST execution time (tLBIST).  
During the start-up phase externally supplied VDD voltage has to be equal or greater than 1.2V (VDD nominal - 4%) for static  
accuracy.  
If VDD is supplied internally by EVRC, EVRC takes care not to violate the VDD 1.2V static under voltage limit.  
3.12.1  
Calculating the 1.25 V Current Consumption  
The current consumption of the 1.25 V rail is composed of two parts:  
Static current consumption  
Dynamic current consumption  
The static current consumption is related to the device temperature TJ and the dynamic current consumption  
depends on the configured clocking frequencies and the software application executed. These two parts need to  
be added in order to get the rail current consumption.  
(3.1)  
mA  
0, 0246 × T  
--------  
C
I
= 5, 8871  
× e  
[C]  
J
0
(3.2)  
mA  
--------  
0, 0232 × T  
I
= 16, 4863  
× e  
[C]  
J
0
C
Equation (3.1) defines the typical static current consumption and Equation (3.2) defines the maximum static  
current consumption. Both functions are valid for VDD = 1.275 V.  
Data Sheet  
452  
V 1.2, 2021-03  
OPEN MARKET VERSION  
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