C167CR
C167SR
AC Characteristics
External Clock Drive XTAL1
(Operating Conditions apply)
Table 11
External Clock Drive Characteristics
Parameter
Symbol
Direct Drive
1:1
Prescaler
2:1
PLL
1:N
Unit
min.
Oscillator period tOSC SR 30
max.
min.
max.
min.
451)
10
10
–
max.
5001) ns
–
–
–
8
8
15
5
–
–
–
5
5
High time2)
Low time2)
Rise time2)
t1
t2
t3
t4
SR 153)
SR 153)
SR –
–
ns
ns
ns
ns
5
–
–
10
10
Fall time2)
SR –
–
–
1)
The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock generation
mode. Please see respective table above.
2)
3)
The clock input signal must reach the defined levels VIL2 and VIH2
.
The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (fCPU) in
direct drive mode depends on the duty cycle of the clock input signal.
t1
t3
t4
VIH2
VIL
0.5 VDD
t2
tOSC
MCT02534
Figure 11
External Clock Drive XTAL1
Note: If the on-chip oscillator is used together with a crystal, the oscillator frequency is
limited to a range of 4 MHz to 40 MHz.
It is strongly recommended to measure the oscillation allowance (or margin) in the
final target system (layout) to determine the optimum parameters for the oscillator
operation. Please refer to the limits specified by the crystal supplier.
When driven by an external clock signal it will accept the specified frequency
range. Operation at lower input frequencies is possible but is guaranteed by
design only (not 100% tested).
Data Sheet
53
V3.2, 2001-07
INFINEON [ Infineon ]
