C167CR
C167SR
for one single TCL (see formula and Figure 10).
For a period of N × TCL the minimum value is computed using the corresponding
deviation D :
N
(N × TCL)min = N × TCLNOM - D
D [ns] = (13.3 + N × 6.3) / fCPU [MHz],
N
N
where N = number of consecutive TCLs and 1 ≤ N ≤ 40.
So for a period of 3 TCLs @ 25 MHz (i.e. N = 3): D = (13.3 + 3 × 6.3) / 25 = 1.288 ns,
3
and (3TCL)min = 3TCLNOM - 1.288 ns = 58.7 ns (@ fCPU = 25 MHz).
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is neglectible.
Note: For all periods longer than 40 TCL the N = 40 value can be used (see Figure 10).
Max. jitter DN
30
10 MHz
26.5
This approximated formula is valid for
ns
20
1
N
40 and 10 MHz fCPU 33 MHz.
16 MHz
20 MHz
25 MHz
33 MHz
10
1
N
1
5
10
20
40
MCD04413
Figure 10
Approximated Maximum Accumulated PLL Jitter
Data Sheet
51
V3.2, 2001-07
INFINEON [ Infineon ]
