SAE 81C90/91
07Feb95@09:05h Intermediate Version
Figure 7
Lengthening a Bit Period
Figure 8
Shortening a Bit Period
Delay Times
The total delay is calculated from the following single delays:
● 2 × physical bus tBus (max. 100 ns acc. to CAN specification)
● 2 × input comparator tComp (depends on application circuit)
● 2 × output driver tDriver (depends on application circuit)
● 1 × input to output of CAN controller tInOut (max. 1 tSCL + 80 ns)
t
Delay = 2 × (tBus + tComp + tDriver) + tInOut
Recommendations
On the premise of the stated conditions, there are the following essential requirements to be
maintained:
tTSeg1
tTSeg1
≥
≥
tSeg2
tDelay
tTSeg2 > tSJW
tTSeg2 3 × tSCL + tSJW
≥
if bit SAM = 1 (otherwise bit recognition does not work).
Semiconductor Group
32
INFINEON [ Infineon ]
