SAE 81C90/91
07Feb95@09:05h Intermediate Version
Time Stamp Register Table
Address
Function
High Byte
Low Byte
High Byte
Low Byte
:
30
H
Time-Stamp 0
Time-Stamp 1
31
H
32
H
33
H
:
:
3C
H
High Byte
Low Byte
High Byte
Low Byte
Time-Stamp 6
3D
H
3E
H
Time-Stamp 7
3F
H
Transmit Check Error Counter
TCEC
7
-
6
-
5
-
4
-
3
-
2
1
TCECV
rw
0
Address: 15
H
Reset Value: 00
-
-
-
-
-
rw
rw
H
Bit(field)
TCECV
Function
Transmit Check Error Counter Value
Number of errors detected by the transmit check unit.
When a count of 4 is reached an interrupt is generated if enabled.
If bit TCE (CTRL.1) is set to ’1’ the Bus Off status is entered in this case.
Note: Not defined bit positions must be ’0’ for write accesses.
Transmit Check Data Register
This register supports an error analysis when a transmit check error is encountered. Reading TCD
provides the byte which was actually being sent when the error occurred.
TCD
7
r
6
r
5
r
4
3
2
r
1
r
0
r
Address: 16
Data Byte
H
Reset Value: XX
r
r
H
Bit(field)
Function
Data Byte
The data byte which was attempted to be sent while a transmit check error was
encountered.
Semiconductor Group
29
INFINEON [ Infineon ]
