SAE 81C90/91
07Feb95@09:05h Intermediate Version
Receive-Ready Registers
RRR2
7
6
5
4
3
2
1
0
Address: 05
RR15
rw
RR14
rw
RR13
rw
RR12
rw
RR11
rw
RR10
rw
RR9
rw
RR8
rw
H
Reset Value: 00
H
RRR1
7
6
5
4
3
2
1
0
Address: 04
RR7
rw
RR6
rw
RR5
rw
RR4
rw
RR3
rw
RR2
rw
RR1
rw
RR0
rw
H
Reset Value: 00
H
Bit(field)
RRn
Function
Receive Ready Bit
’0’: No new message received in object n.
’1’: A new message has been received and stored in object n.
These register bits can be reset by writing ’0’ to the respective bit, writing ’1’ has no effect. Bit RRn
is set when a message has arrived and been written into the memory location of message n. Setting
this bit by hardware can generate a receive interrupt, which can be blocked by bit RIMn in the
receive-interrupt-mask register.
Bits RRn must be reset by software.
Receive-Interrupt-Mask Registers
Setting bit RIMn enables a receive interrupt to be generated if the receive-ready bit RRn has been
set, i.e. a message has arrived and was written into the memory location of message n.
RIMR2
7
6
5
4
3
2
1
0
Address: 07
RIM15 RIM14 RIM13 RIM12 RIM11 RIM10
RIM9
rw
RIM8
rw
H
Reset Value: 00
rw
rw
rw
rw
rw
rw
H
RIMR1
7
6
5
4
3
2
1
0
Address: 06
RIM7
rw
RIM6
rw
RIM5
rw
RIM4
rw
RIM3
rw
RIM2
rw
RIM1
rw
RIM0
rw
H
Reset Value: 00
H
Bit(field)
RIMn
Function
Receive Interrupt Mask Bit
’0’: No interrupt upon reception of object n.
’1’: When a new message is stored in object n an interrupt is generated.
Note: Bit ERI in the interrupt-mask register IM blocks all receive interrupts, even if bits RIMn are
set.
Semiconductor Group
25
INFINEON [ Infineon ]
