SAE 81C90/91
07Feb95@09:05h Intermediate Version
Transmit Request Registers
The Transmit Request Set Registers provide a transmission request bit (TRSn) for each message
object. Setting a transmission request bit causes the respective message x to be transmitted. The
bit is cleared by hardware after transmission. Several bits can be set simultaneously. In this way all
messages whose request bits are set are transmitted in turn, starting with the memory location with
the highest number.
Note: A transmission request bit is set by writing ’1’ to the respective bit location (TRSn). Writing ’0’
has no effect.
TRSR2
7
6
5
4
3
2
1
0
Address: 09
TRS15 TRS14 TRS13 TRS12 TRS11 TRS10 TRS9
TRS8
rw
H
Reset Value: 00
rw
rw
rw
rw
rw
rw
rw
H
TRSR1
7
6
5
4
3
2
1
0
Address: 08
TRS7
rw
TRS6
rw
TRS5
rw
TRS4
rw
TRS3
rw
TRS2
rw
TRS1
rw
TRS0
rw
H
Reset Value: 00
H
Bit(field)
TRSn
Function
Transmit Request Set Bit
’0’: No change of the respective transmit request bit.
’1’: The respective transmit request bit is cleared.
n = 0...15
The Transmit Request Reset Registers provide a transmit request reset bit (TRRn) for each
transmit request bit TRSn, i.e. for each message object.
Writing ’1’ to a TRRn bit clears the corresponding transmission request bit TRSn. This causes a
transmission request, initiated by the corresponding bit TRSn, to be cancelled, provided that it is not
currently processed.
This scheme avoids conflicts when writing to register bits while they are cleared by hardware
because of a completed transmission.
Note: Registers TRRRx cannot be read.
Semiconductor Group
26
INFINEON [ Infineon ]
