SAE 81C90/91
07Feb95@09:05h Intermediate Version
Register Map (ordered by address)
Addr. Reg. Name Reset Addr. Reg. Name Reset
Addr. Reg. Name Reset
00
01
02
03
04
05
06
07
BL1
00
00
00
00
00
00
00
00
20
21
22
23
24
25
26
27
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
40
41
42
43
44
45
46
47
DR0H
DR0L
DR1H
DR1L
DR2H
DR2L
DR3H
DR3L
UU
UU
UU
UU
UU
UU
UU
UU
---
---
---
---
---
---
---
---
00
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
BL2
OC
BRP
RRR1
RRR2
RIMR1
RIMR2
08
09
TRS1
00
00
00
28
29
P0PDR
P0PR
48
49
DR4H
DR4L
DR5H
DR5L
UU
UU
UU
UU
H
H
H
H
H
H
H
H
H
H
H
H
H
H
TRS2
XX
00
H
0A
IMSK
2A
P0LR
4A
H
H
H
H
H
H
H
0B
Reserved
2B
Reserved
4B
---
---
---
---
---
---
0C
0D
0E
Reserved
Reserved
Reserved
Reserved
2C
2D
2E
P1PDR
P1PR
00
4C
4D
4E
DR6H
DR6L
DR7H
DR7L
UU
UU
UU
UU
H
H
H
H
H
H
H
H
H
XX
00
H
H
H
P1LR
H
H
H
H
H
H
H
0F
2F
Reserved
4F
---
10
MOD
00
30
TSR0H
TSR0L
TSR1H
TSR1L
UU
UU
UU
UU
50
DR8H
DR8L
DR9H
DR9L
UU
UU
UU
UU
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
11
12
13
INT
00
00
31
32
33
51
52
53
H
H
CTRL
Reserved
---
14
15
16
17
CC
01
34
35
36
37
TSR2H
TSR2L
TSR3H
TSR3L
UU
UU
UU
UU
54
55
56
57
DR10H
DR10L
DR11H
DR11L
UU
UU
UU
UU
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
TCEC
TCD
00
H
XX
---
00
H
Reserved
18
19
TRR1
38
39
TSR4H
TSR4L
TSR5H
TSR5L
TSR6H
TSR6L
TSR7H
UU
UU
UU
UU
UU
UU
UU
58
59
DR12H
DR12L
DR13H
DR13L
DR14H
DR14L
DR15H
UU
UU
UU
UU
UU
UU
UU
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
TRR2
00
00
00
00
00
H
1A
1B
RRP1
RRP2
TSCH
TSCL
3A
3B
5A
5B
H
H
H
H
H
H
H
H
H
H
1C
1D
1E
3C
3D
3E
5C
5D
5E
H
H
H
H
H
H
Reserved
---
---
H
H
H
H
H
H
1F
Reserved
3F
TSR7L
UU
5F
DR15L
UU
H
H
Note: The locations marked “UU ” are not changed upon a reset.
H
After a power on reset they are undefined (XX ), of course.
H
Semiconductor Group
12
INFINEON [ Infineon ]
