PEB 2091
PEF 2091
Operational Description
4.1.4.1 Monitor Channel Protocol
The PI allows to program the IEC-Q Monitor Channel in the way known from the PEB
2070 (ICC).
The Monitor Channel operates on an asynchronous basis. While data transfers on the
IOM®-2-bus occur synchronized to frame sync FSC, the flow of data is controlled by a
handshake procedure using the Monitor Channel Receive (MR) and Monitor Channel
Transmit (MX) bits. For example: data is placed onto the Monitor Channel and the MX
bit is activated. This data will be transmitted repeatedly once per 8-kHz frame until the
transfer is acknowledged via the MR bit.
The microprocessor may either enforce a "1" (idle) in MR, MX by setting the control bit
MOCR:MRC or MOCR:MXC to "0", or enable the control of these bits internally by the
IEC-Q according to the Monitor Channel protocol. Thus, before a data exchange can
begin, the control bits MRC or MXC should be set to "1" by the microprocessor.
The Monitor Channel protocol is illustrated in Figure 43. The relevant control and status
bits for transmission and reception are:
Table 16
Register
MOCR
Monitor Transmit Bits
Bit
control / status Function
MXC
MXE
MDA
MAB
MAC
control
MX Bit Control
Transmit Interrupt Enable
Data Acknowledged
Data Abort
MOSR
STAR
status
Transmission Active
Table 17
Register
MOCR
Monitor Receive Bits
Bit
control / status
Function
MRC
MRE
MDR
MER
control
MR Bit Control
Receive Interrupt Enable
Data Received
End of Reception
MOSR
status
Semiconductor Group
103
Data Sheet 01.99
INFINEON [ Infineon ]
