PEB 2091
PEF 2091
Register Description
5.2.12
SWST-Register
Write
Address F
H
The Switch Status Register (SWST) selects the switching directions of the processor
interface (PI).
Reset value: 00H
7
6
5
4
3
2
1
0
WT
B1
B2
D
CI
MON
BS
SGL
WT
B1
Watchdog Timer
1=
0=
Enables the watchdog timer (see "Watchdog Timer", page 93)
Disables the watchdog timer
B1-channel Processing
1=
Enables the microprocessor to access B1-channel data between
IOM®-2 and the transceiver core
0=
Disables the function described above
B2
D
B2-channel Processing
1=
Enables the microprocessor to access B2-channel data between
IOM®-2 and the transceiver core
0=
Disables the function described above
D-channel Processing
1=
Enables the microprocessor to access D-channel data between
IOM®-2 and transceiver core
0=
Disables the function described above
CI
C/I-channel Processing
1=
Enables the microprocessor to access C/I-commands and indications
between IOM®-2 and transceiver core
Disables the function described above
0=
MON
Monitor-channel Processing
1=
Enables the microprocessor to access Monitor-channel messages at
IOM®-2 and at the transceiver core
Disables the function described above
0=
Semiconductor Group
220
Data Sheet 01.99
INFINEON [ Infineon ]
