PEB 2091
PEF 2091
Register Description
5.2.6
MOCR-Register
Write
Address A
H
The Monitor Control Register (MOCR) allows to program and control the Monitor channel
as described in the section 5.1.1.
Reset value: 00H
7
6
5
4
3
1
2
1
1
1
0
1
MRE
MRC
MXE
MXC
MRE Monitor Receive Interrupt Enable
1=
Enables the Monitor data receive (MDR) interrupt status bit; MRE = 1
enables the Monitor data receive (MDR) and the Monitor end of
reception (MER) interrupt status bits
0=
Masks the MDR and the MER bits
MRC Monitor Channel Receive Control
1=
Enables the control of the MR bit internally by the IEC-Q according to
the Monitor channel protocol
0=
Enforces a "1" (inactive state) in the Monitor channel receive (MR) bit
MXE Monitor Transmit Interrupt Enable
1=
Combined with the MXC bit tied to "1" enable the Monitor channel data
acknowledged (MDA) and the Monitor channel data abort (MAB)
interrupt status bits
0=
Masks the MDA and the MAB bits
MXC Monitor Channel Transmit Control
1=
Enables the control of the MX bit internally by the IEC-Q according to
the Monitor channel protocol
0=
Enforces a "1" (inactive state) in the Monitor channel transmit (MX) bit
Semiconductor Group
216
Data Sheet 01.99
INFINEON [ Infineon ]
