PEB 2091
PEF 2091
Register Description
BS
BS Bit
Operates in combination with SWST:SGL and ADF:CBAC bits to control the
S/G bit and the BAC bit. For the functional description see "Indication of S/G
Bit Status on Pin SG", page 205
SGL
Stop/Go
Operates in combination with SWST:BS and ADF:CBAC bits to control the S/G
bit and the BAC bit. For the functional description see "Indication of S/G Bit
Status on Pin SG", page 205
5.2.13
B-Channel Access Registers
Register
Value after Function
reset (hex)
Address
(hex)
WB1U
RB1U
WB1I
RB1I
00
00
00
00
00
00
00
00
write B1-channel data to transceiver core
6
read B1-channel data from transceiver core 6
write B1-channel data to IOM®-2
read B1-channel data from IOM®-2
8
8
7
WB2U
RB2U
WB2I
RB2I
write B2-channel data to transceiver core
read B2-channel data from transceiver core 7
write B2-channel data to IOM®-2
read B2-channel data from IOM®-2
9
9
5.2.14
D-Channel Access Registers
Register
Value after Function
Reset (hex)
Address
(hex)
DWU
DRU
DWI
DRI
FF
FF
FF
FF
write D-channel data to transceiver core
3
3
read D-channel data from transceiver core
write D-channel data to IOM®-2
read D-channel data from IOM®-2
B
B
Semiconductor Group
221
Data Sheet 01.99
INFINEON [ Infineon ]
