PEB 2091
PEF 2091
Register Description
5.2.11
ADF-Register
Write
Address E
H
Additional Features Register (ADF).
Reset value: 14H
7
6
5
4
3
1
2
1
0
WTC2 WTC1 PCL1 PCL0
UVD
BCL CBAC
WTC2, WTC1 Watchdog Controller
The bit patterns "10" and "01" has to be written in WTC1 and WTC2 by
the enabled watchdog timer within 132ms. If it fails to do so, a reset
signal of 5ms at pin RST is generated
PCL1, PCL0
Prescaler
The clock frequency on MCLK is selected by setting the bits according
to the table below:
PCL1
PCL0
Frequency at
MCLK (MHz)
0
0
I
0
I
7.68
3.84
1.92
0.96
0
I
I
UVD
Undervoltage Detector
1=
Enables the undervoltage detector. For details see
"Undervoltage Detection", page 92
0=
Disables the undervoltage detector
BCL
Bit Clock
1=
0=
Changes the DCL-output into the bit-clock mode
Gives the doubled bit clock on the DCL-output
CBAC
Control BAC
Operates in combination with SWST:SGL and SWST:BS bits to
control the S/G bit and the BAC bit. For the operational description see
"S/G Bit and BAC Bit Operations", page 198
Semiconductor Group
219
Data Sheet 01.99
INFINEON [ Infineon ]
