PEB 2091
PEF 2091
Operational Description
µ
P
Transmitter
MON
Receiver
MR
µ P
MX
MRE= 1
125 µ s
FF
1
1
0
1
1
1
MXE = 1
MOX = ADR
MXC = 1
FF
ADR
MDR Int.
RD MOR (= ADR)
MRC = 1
MAC = 1
ADR
0
1
0
0
0
0
MDA Int.
MOX = DATA1
DATA1
DATA1
MDR Int.
RD MOR (= DATA1)
DATA1
DATA1
0
0
1
0
MDA Int.
MOX = DATA2
DATA2
DATA2
1
0
0
0
MDR Int.
RD MOR (= DATA2)
DATA2
DATA2
0
0
1
0
MDA Int.
MXC = 0
FF
FF
1
1
0
0
MER Int.
MRC = 0
FF
FF
1
1
1
1
MAC = 0
ITD08119
Figure 43
Monitor Channel Protocol
Before starting a transmission, the microprocessor should verify that the transmitter is
inactive, i.e. that a possible previous transmission has been terminated. This is indicated
by a "0" in MOSR:MAC, the Monitor Channel Active status bit.
To enable interrupts for the transmitter the MOCR:MXE bit must be set to "1" (For details
see "Monitor-Channel Interrupt Logic", page 209). After having written the Monitor Data
Transmit (MOX) register, the microprocessor sets the Monitor Transmit Control bit MXC
to "1". This enables the MX bit to go active ("0"), indicating the presence of valid Monitor
data (contents of MOX) in the corresponding frame. As a result, the receiving device
stores the Monitor byte in its Monitor Receive (MOR) register and generates an MDR
interrupt status.
Semiconductor Group
104
Data Sheet 01.99
INFINEON [ Infineon ]
