Register Description
BAS
Bus Access Status
Indicates the state of the TIC-bus:
0: the ISAC-S itself occupies the D and C/I channel
1: another device occupies the D and C/I channel
CODR C/I Code Receive
Value of the received Command/Indication code. A C/I code is loaded in CODR only
after being the same in two consecutive IOM frames and the previous code has been
read from CIRR.
(refer to chapter 3.3.2)
C/I Code Change
CIC0
A change in the received Command/Indication code has been recognized. This bit is
set only when a new code is detected in two consecutive IOM frames. It is reset by a
read of CIRR.
Note: The BAS and CODR bits are updated every time a new C/I code is detected in two
consecutive IOM frames.
If several consecutive codes are detected and CIRR is not read, only the first and the
last C/I code (and BAS bit) is made available in CIRR at the first and second read of
that register, respectively.
4.2.3
Command/Indication Transmit RegisterCIXR
Write
Address 31
H
Value after reset: 3C
H
7
0
RSS
BAC
TCX
ECX
CODX
RSS
Reset Source Select
Only valid if the terminal specific functions are activated (STCR:TSF).
0 : Subscriber or Exchange Awake
As reset source serves:
– a falling edge on the EAW line (External Subscriber Awake)
– a C/I code change (Exchange Awake).
A logical zero on the EAW line activates also the IOM-interface clock and frame
signal, just as the SPU-bit (SPCR) does.
Semiconductor Group
221
INFINEON [ Infineon ]
